1. Field of the Invention
The present invention relates to the prevention of reverse engineering of integrated circuits, and more particularly to an integrated circuit structure comprising a programmable connector/isolator between polysilicon (i.e. polycrystalline silicon) and source/drain N+ or P+ regions, to be used in a MOS-type circuit, like nMOS, pMOS or CMOS.
2. Description of the Related Art
The design, development and manufacturing efforts pertaining to semiconductor integrated circuits involve the understanding of complex structures, processes and manufacturing techniques involving smaller and smaller electronic circuitry. Efforts to be able to achieve such understanding and establish successful design, development and production manufacturing of such integrated circuits involve many man-hours of highly skilled professionals and considerable expense.
On the other hand, to avoid costly man-hours and other significant expenses some developers resort to reverse engineering practices wherein existing devices are taken apart, probed and otherwise examined to determine the physical structures of the resultant integrated circuit under review for subsequent copying. This reverse engineering, which typically relies primarily on obtaining planar optical image of the circuit, in essence attempts to by-pass typical product development efforts and expenses by studying and copying a competitive product.
Various approaches have been developed in an attempt to thwart such reverse engineering efforts, particularly in the field of semiconductor integrated circuits.
For example, U.S. Pat. No. 5,866,933 in the name of the same inventors of the present application teaches how transistors in a CMOS circuit can be connected by hidden lines between the transistors, via modifying the P+ and N+ source/drain masks. These implanted interconnections are further used to make a 3-input AND and OR circuit look substantially the same.
Moreover, U.S. Pat. No. 5,783,846 in the name of the same inventors of the present application teaches a further modification in the source/drain implant masks so that the implanted connecting lines between transistors have a gap inserted, the length of which is approximately the length of the feature size of the CMOS technology being used. If the gap is “filled” with one kind of implant (depending on the implanted connecting line being p or n) the line conducts. But, if the gap is filled with the other kind of implant the line does not conduct. These gaps are called “channel blocks”. Thereby the reverse engineer must determine connectivity on the basis of resolving the n or p implant at the minimum feature size of the channel block. Moreover, transistor sizes and metal connection routings are modified, to eliminate keys by which the reverse engineer can find inputs, outputs, gate lines etc. as keys to the circuit functionality.
Hence, the reverse engineer is forced to examine every transistor within the IC to determine functionality and connectivity, so that he is prevented from making effective progress. In this way, the task for the reverse engineer to discover the entire functionality of an IC containing many tens of thousands transistors is clearly impractical.
However, the modern reverse engineer has many tools to automate the viewing and analysis of the planar images of the IC. Automatic pattern recognition techniques, applied to the metal and polysilicon routing lines in the circuit, can be very effective.